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[VHDL-FPGA-Verilog] Buf_FiFo

Description: verilog 编写的FIFO，里边有IP核和控制模块，-verilog write FIFO, inside the IP core and control module,
Platform: | Size: 5120 | Author: 王红伟 | Hits:

[Program doc] Cy7C68013_SLAVE-FIFO_Verilog

Description: 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code
Platform: | Size: 1191936 | Author: 王大锤 | Hits:

[VHDL-FPGA-Verilog] VerilogBasicICDesign

Description: Verilog基本电路设计,包括时钟域同步、无缝切换、 异步FIFO、去抖滤波-Verilog basic circuit design, including clock domain synchronization, seamless switching, asynchronous FIFO, debounce filter
Platform: | Size: 6144 | Author: 韩向超 | Hits:

[Mathimatics-Numerical algorithms] async_fifo

Description: system verilog environment for asynchornous FIFO
Platform: | Size: 63488 | Author: rohit | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。-uart communication
Platform: | Size: 256000 | Author: 曹振吉 | Hits:

[VHDL-FPGA-Verilog] arinc429_transmitter

Description: Simple Arinc-429 transmitter channel description on Verilog HDL with parameterized DATA FIFO.
Platform: | Size: 4096 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] apb_spi

Description: Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
Platform: | Size: 11264 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。（不能直接使用。）-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
Platform: | Size: 1024 | Author: 刘宇洋 | Hits:

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

[Other] oscillo_1

Description: 简单数字示波器的verilog设计,涉及到时钟同步，FIFO的配置和使用，非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)
Platform: | Size: 5110784 | Author: Ianlovelynn | Hits:

[VHDL-FPGA-Verilog] uart_design

Description: UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
Platform: | Size: 547840 | Author: 沐羽1996 | Hits:
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